ASSP/ASIC/FPGA Intellectual Property (IP) Modules:

Multi-Media (MMC) Card & Secure Digital (SD) Card Controller

This product has been architected to serve as a peripheral to a microcontroller and/or DSP based System-on-a-Chip (SoC). It generates the proper commands to the cards and pass the data back and forth following the MMC or SD protocol specifications.
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External Memory Interface (EMIF)

External Memory Interface (EMIF) to three of the most popular types of memories being used in Systems-on-a-Chip (SoC) platforms: SRAM, SDRAM, and FLASH. Provides glue less connectivity for up to 512KB of external memory addressing space. Provides different addressing modes for either 8 or 16 bit memory devices.
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Advanced Encryption Standard (AES) Co-Processor

A novel minimum cost architecture for the Advanced Encryption Standard (AES) algorithm. This architecture uses a bit-serial approach, and it is suitable for VLSI implementations. By utilizing a true bit-serial design, this architecture can be used for cost sensitive applications that require high security, such as security system human interfaces, point of sale terminals, and infotainment kiosks. This AES architecture can be used as a coprocessor integrated with an inexpensive microcontroller in a system-on-a-chip (SoC) platform.
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Local Interconnect Network (LIN) Slave Peripheral

This module implements a digital slave controller for the LIN bus used in automotive applications. It is compatible with the LIN Specification Package 2.0, LIN Specification Package 1.3, and the SAE J2602 Recommended Practice for LIN.
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Infrared Data Association (IrDA) Peripheral Controller

This module implements the data link layer (OSI layer 2) functions, features, protocol compliant with the Serial Infrared Link Access Protocol (IrLAP) specification (version 1.1)
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Floating Point Arithmetic Modules

Various arithmetic functions (addition, subtraction, multiplication, division, square) for single and double precision IEEE Floating Point Standard with different level of pipelining to meet different systems requirements.
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Data Clustering Architecture

High performance architecture for the important task of unsupervised data clustering in computer vision applications. This architecture exploits paradigms of connectivity, parallelism, and functionality like those inspired by neural networks. By utilizing a "global-systolic, local-hyper-connected" architectural approach, this architecture can be suitable for the processing of real time DVD quality video at the highest rate allowed by the MPEG-2 standard.
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Markov Random Field (MRF) Parameters Computation Module

Architecture for the computation of MRF parameters.
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